Alternative flip chip in leaded molded package design and method for manufacture

ABSTRACT

A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach region and is within the window. A gap is present between the edge of the semiconductor die and the molding material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a divisional patent application of U.S.patent application Ser. No. 10/772,064, filed Feb. 3, 2004, which is anon-provisional patent application of U.S. patent application Ser. No.60/446,918, filed Feb. 11, 2003, which are herein incorporated byreference in their entirety for all purposes.

BACKGROUND OF THE INVENTION

A Flipchip in Leaded Molded Package (FLMP) is described in U.S. patentapplication Ser. No. 09/464,717. In a conventional FLMP package, thebackside of a silicon die is exposed through a window in a moldingmaterial. The backside of the die can be in substantially direct thermaland electrical contact with a circuit substrate such as a PC board.

When the FLMP package is made, a molding process is performed after thedie is attached to a leadframe structure. To keep the backside of thedie clean from mold bleed or mold flash, the package is designed so thatno gap is present between the mold cavity and the backside of silicondie. During manufacture, the die is contacted by a mold tool upon moldtool clamping. Since the die is brittle and since the package is thin,the potential for breakage of the die and disconnection between the dieand the leadframe is of concern.

Embodiments of the invention address these and other problems.

SUMMARY OF THE INVENTION

Embodiments of the invention are directed to semiconductor packages andmethods for making semiconductor packages.

One embodiment of the invention is directed to a method for making asemiconductor package comprising: (a) molding a molding material arounda leadframe structure having a die attach region and a plurality ofleads, wherein the die attach region is exposed through a window in themolding material; and (b) after (a), mounting a semiconductor die to thedie attach region using a flip chip mounting process.

Another embodiment of the invention is directed to a semiconductorpackage comprising: (a) a leadframe structure comprising a die attachregion and plurality of leads; (b) a molding material molded around atleast a portion of the leadframe structure, and wherein the moldingmaterial comprises a window; and (c) a semiconductor die mounted on thedie attach region.

Another embodiment of the invention is directed to an electricalassembly comprising: a semiconductor package comprising (a) a leadframestructure comprising a die attach region and plurality of leads, (b) amolding material molded around at least a portion of the leadframestructure and wherein the molding material comprises a window, and (c) asemiconductor die comprising an edge mounted on the die attach region,wherein the semiconductor die is within the window, and wherein a gap ispresent between the edge and the molding material; and a circuitsubstrate, wherein the semiconductor package is mounted to the circuitsubstrate.

These and other embodiments of the invention are described in furtherdetail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1(a) shows a top perspective view of a semiconductor packageaccording to an embodiment of the invention.

FIG. 1(b) shows a bottom perspective view of the package in FIG. 1(a).

FIG. 1(c) shows a side cross-sectional view of the semiconductor packagein FIGS. 1(a) and 1(b) mounted on a circuit substrate.

FIG. 1(d) shows a package configuration with only one die.

FIG. 2 shows a package configuration with two dies.

FIG. 3(a) shows a top perspective view of the package according toanother embodiment of the invention.

FIG. 3(b) shows a bottom perspective view of the package in FIG. 3(a).

FIG. 3(c) shows a top perspective view the package in FIG. 3(a) with aheat plate structure.

FIG. 3(d) shows a side cross-sectional view of the package in FIGS. 3(a)and 3(b).

FIGS. 4(a)-4(f) show various illustrations of a package as it is beingformed.

FIG. 5 shows an exploded view of a package according to an embodiment ofthe invention.

These and other embodiments are described in further detail below in theDetailed Description.

DETAILED DESCRIPTION

Embodiments of the invention are directed to an alternative design andmethod of manufacture for an FLMP package. In embodiments of theinvention, mechanical stress experienced by a semiconductor die during amolding process is substantially eliminated. As indicated above,mechanical stress during the process of manufacturing a package can leadto die cracking or solder cracking. Embodiments of the invention alsoeliminate the possibility of mold bleed or mold resin contamination onan exposed backside of a die. Using embodiments of the invention, it ispossible to create thinner packages (e.g., less than about 0.5 mm inheight) where it is difficult to do so in a standard FLMP manufacturingmethod. In some embodiments, an opening at the top surface of thepackage also provides for optional use of an additional heat sink suchas a heat plate structure to provide for better thermal dissipation.

The semiconductor package may use a pre-plated and/or pre-formed copperbased leadframe structure, a pre-molding technique that produces apremolded leadframe structure, a solder bumped or non-solder bumpedsemiconductor die, and an intermediate solder paste. The details andbenefits of using each of these features are explained below.

First, copper is an excellent electrical and thermal conductor so copperleadframe structures are preferred in embodiments of the invention. Insome embodiments, the leadframe structure may be preplated with metalssuch as NiPdAu. Pre-plating the leadframe structure reduces thepackage's exposure to chemicals, since the finished package need not beexposed to chemicals such as plating chemicals after it is formed.Pre-plating a leadframe structure also allows one to subject theleadframe structure to high reflow temperatures without melting.Pre-forming the leadframe structure also eliminates the mechanicalstresses to be absorbed by the package due to the leadforming process.

Second, a pre-molding technique may be used to form a pre-moldedleadframe structure in embodiments of the invention. The premoldedleadframe structure is a desirable feature of embodiments of theinvention. In the premolded leadframe structure, the leadframe structureand the molding material can be locked together. The premolded leadframestructure can provide for an exposed leadframe surface for dieattachment without using any film or tape. It is possible to maintaindie backside planarity with respect to the exposed leads of theleadframe structure depending on the package configuration for thedrain, gate and source connections to the circuit substrate (e.g., a PCboard). The premolded leadframe structure includes a first window forreceiving a die, and an optional second window for receiving a heat sinksuch as a heat plate structure (for further thermal dissipation).

Third, an array of bumps in the die may serve as the source and gateelectrical terminals for a transistor die. They also serve as mechanicaland thermal stress absorbers between the die and the leadframestructure. In the conventional FLMP package, the bumps are tall so thatenough space is provided for a molding material to flow between thesilicon die and the leadframe structure. A soft solder bump material isalso ideal for a standard FLMP package to minimize the compressionstress that is absorbed by the die during the molding process. Incomparison, in embodiments of the invention, any bump material andshorter heights can be used, since molding is performed before dieattachment to the leadframe structure. The materials and heights of thebumps are independent of molding process considerations.

In embodiments of the invention, the package can use silicon dies withthicknesses down to 0.10 mm. Also, solder paste is used to couple thebumps on a die (especially for non-solder bumps) to the leadframestructure to provide for an electrical and mechanical connection. Thebumps, and solder paste can be Pb-based or Pb-free solder materials,with melting temperatures above 260° C. in some embodiments. The bumpscan comprise a non-solder material like copper and gold.

Embodiments of the invention also provide for leadframe structurevariations to meet desired electrical pin-out configurations and toallow for multiple dies in a single package. Embodiments of theinvention also provide for a top window opening in the molding materialto provide for a heatsink option. In some embodiments, it is alsopossible to use a thinner leadframe structure, a thinner moldingmaterial, a thinner die, and shorter bumps so that a package that is0.50 mm or less in thickness can be produced.

FIG. 1(a) shows a package 100 according to an embodiment of theinvention. The package 100 includes a molding material 22 with two holes20 at the top of the package 100. The holes 20 may be provided to allowfor better thermal dissipation from the die that is in the package 100.Any suitable molding material 22 including, for example, an epoxymolding material may be used. The package 100 also includes a number ofleads 24 including a gate lead 24(g) and a plurality of source leads24(s). The illustrated package 100 has 7 source leads and one gate lead.Other package embodiments may have more or less leads.

The leads 24 in the package 100 may be part of a leadframe structure. Asused herein, the term “leadframe structure” can refer to a structurethat is derived from a leadframe. A typical leadframe structure includesa source lead structure, and a gate lead structure. Each of the sourcelead structure and the gate lead structure can have one or more leads.

FIG. 1(b) shows a bottom side view of the package 100. The package 100includes a semiconductor die 30. A backside 30(a) of the semiconductordie 30 may show through a window in the molding material 22. Thebackside 30(a) of the die 30 corresponding to the drain region of atransistor in the die 30 may be metallized and may be distal to a dieattach region of the leadframe structure. The opposite frontside of thedie 30 may correspond or include a source region and a gate region andmay be proximate to the die attach region of the leadframe structure.The die backside 30(a) provides for an electrical terminal, and may becoplanar with the bottom surface of the molding material 22 and coplanarwith the ends of the leads 24. The window in the molding material 22 isslightly larger than the outer edges (and planar dimensions) of the die30.

A small gap 11 is present between the molding material 22 and the outeredges of the die 30. This small gap 11 also allows the die 30 tothermally expand and contract independently of the molding material 22.As shown, the gap 11 may extend around the entire periphery of the die30. No molding material is present between the solder joints couplingthe leadframe structure and the die 30.

FIG. 1(c) shows a side cross-sectional view of an electrical assembly103. The package 100 shown in FIGS. 1(a) and 1(b) is mounted on acircuit substrate 55 in FIG. 1(c). Solder (not shown) such as 63Sn/37Pbmay be used to electrically couple the backside of the die 30 and theends of the leads 24 to one or more conductive regions in the circuitsubstrate 55. As shown therein, a small gap 11 is present between themolding material 22 and the outer edges of the die 30.

FIG. 1(d) shows the leadframe structure 38. Bumps 34 are also shownattaching the die 30 to the leadframe structure 36. Apertures 38 may bepresent in the leadframe structure 36 to allow a molding material 22 toflow through and lock to the leadframe structure 36.

The semiconductor dies used in the semiconductor packages according topreferred embodiments of the invention include vertical powertransistors. Vertical power transistors include VDMOS transistors. AVDMOS transistor is a MOSFET that has two or more semiconductor regionsformed by diffusion. It has a source region, a drain region, and a gate.The device is vertical in that the source region and the drain regionare at opposite surfaces of the semiconductor die. The gate may be atrenched gate structure or a planar gate structure, and is formed at thesame surface as the source region. Trenched gate structures arepreferred, since trenched gate structures are narrower and occupy lessspace than planar gate structures. During operation, the current flowfrom the source region to the drain region in a VDMOS device issubstantially perpendicular to the die surfaces.

FIG. 2 shows a package 101 with two semiconductor dies 30(a), 30(b) andtwo corresponding leadframe structures 36(a), 36(b) within a singlemolding material. Each leadframe structure 36(a), 36(b) includes a gatelead and a plurality of source leads. Apertures 38 are in the die attachregions of the leadframe structures 36(a), 36(b). In other embodiments,there could be even more leadframe structures and even more dies perpackage.

FIG. 3(a) shows a top view of another embodiment of the invention. Thepackage 100 includes a top window 58 in a molding material 22 thatexposes the top surface 24(x) of a leadframe structure 24. The topsurface 24(x) may be the surface that is opposite to the surface towhich the die is attached.

FIG. 3(b) shows a bottom side view of the package 100 shown in FIG.3(a). The package 100 includes a die 30 that is in another window in themolding material 22. As shown, the backside 30(a) of the die is exposedthrough the molding material 22. Thus, the package 100 may have firstand second windows at opposite sides of the package 100.

FIG. 3(c) shows a metal plate structure 52 that is coupled to the topsurface 24(x) of the leadframe structure 24. As shown, the metal platestructure 52 has a first portion that is planar and is coupled to thetop surface 24(x) of the leadframe structure and has a leg that extendsdown the side of the package 100. The leg of the metal plate structure52 may provide for an additional electrical and/or thermal connectionfor the package 100 to an underlying circuit substrate (not shown).

FIG. 3(d) shows a side cross-sectional view of the package 100, withouta metal plate structure. As shown, a gap 15 is presented between theouter edges of the die 30 and the molding material 22. As shown, thebottom surface of the molding material 22 is coplanar with the diebackside 30(a) and the ends of the leads 24(s). Also, as shown in FIG.3(d), there is no molding material between the joints coupling theleadframe structure and the die 30.

The above-described embodiments may be manufactured in any suitablemanner. For example, a first process flow option may include thefollowing processes: 1. pre-mold/degate/deflash processes, 2. a waterjet deflash process, 3. solder dispense/flipchip attach processes, and4. a reflow process. The reflow process may be followed by: A.leadcut/test/mark processes, and B. singulate/tape and reel processes.The reflow process may alternatively be followed bysingulate/test/mark/tape and reel processes. In another example, asecond process flow option is as follows: 1.pre-mold/degate/deflash/leadcut processes, 2. solder dispense/flipchipattach processes, and 3. a reflow process. The reflow process may befurther followed by A. a test/mark process, and B. singulate/tape andreel processes. The IR reflow process may alternatively be followed bysingulate/test/mark/tape and reel processes. These individual processesare known to those of ordinary skill in the art.

Referring to FIGS. 4(a) to 4(e), the first step is to mold the moldingmaterial 22 onto the leadframe structure 24. Referring to FIG. 4(a), theleadframe structure 24 is loaded into a mold tool 60 with a cavitydesigned to meet the intended predefined package thickness, form andleadframe exposure. A molding material is allowed to liquify, and entersthe mold cavity and solidifies between the molding dies of the mold tool60. After molding, the formed molded strip (if the leadframe is one ofmany leadframes in a strip of leadframes) goes through a degate/deflashprocess to remove the excess mold on the leads or leadframe structures.If the molded strip requires further cleaning, the molded strip canundergo a water jet deflash process. If no further cleaning is required,one process option is to completely cut all extended leads leaving thetiebars connected to the sides of the die attach pads of the leadframestructures. This can be done prior to the attachment of thesemiconductor dies to the leadframe structures.

A molded leadframe structure 99 is shown in FIG. 4(b) and includes amolding material 22 and a leadframe structure. As shown, a relativelylarge window 98 for receiving a die is in the molding material 22. Thewindow 98 exposes the die attach region 97 of the leadframe structure24.

Referring to FIG. 4(c), a solder dispensing process and a flip chipattach process may be performed. The bump 34(a) comprising, for example,95Pb/5Sn may be deposited on the die 30 in a first array. The soldermaterial 34(b) comprising, for example, 88Pb/10Sn/2Ag may be depositedon the exposed surface of the die attach region of the leadframestructure 24 in a second array. The bump material 34(a) may have ahigher melting temperature than the solder paste material 34(b). (Thesolder that is used to attach the finished package to a circuitsubstrate may have a lower melting temperature than either the bump orthe solder paste materials.) As shown in FIG. 4(c), the bumped die 30 isflipped over and the arrays of bumps and solder paste materials 34(a),34(b) are aligned and joined to form an array of joints joining theleadframe structure 24 and the die 30. As shown, the semiconductor die30 fits within the window in the molding material 22 and a small gap isbetween the die 30 and the edges of the window in the molding material22. The backside of the die 30 does not have any residual moldingmaterial, since the molding process was already performed.

As shown in FIG. 4(d), after the die is attached to the leadframestructure, the combination goes to a reflow oven to melt the solderpaste and cohesively attach the bumped silicon die to the pre-moldedleadframe. Suitable reflow temperatures can be chosen by those of skillin the art.

Referring to FIGS. 4(e) and 4(f), electrical testing and furtherprocessing can be done. A first approach is to perform strip testing andmarking before performing singulation and then tape and reel processes.If the leads are still not cut, lead cutting can be done prior to striptesting. The second approach is to perform leadcut and singulationprocesses first, and then to do unit testing and marking beforeperforming a tape and reel process. FIG. 4(f) shows a package in a tapeand reel process.

FIG. 5 shows an exploded view of a package. As shown, the packageincludes a molding material 22 that is coupled to a leadframe structure24. A semiconductor die 30 with an array of bumps 34(a) is coupled tothe leadframe structure 24 with a solder paste material 34(b).

It is noted that the present invention is not limited to the preferredembodiments described above, and it is apparent that variations andmodifications by those skilled in the art can be performed within thespirit and scope of the present invention. Moreover, any one or moreembodiment of the invention may be combined with one or more embodimentsof the invention without departing from the spirit and scope of theinvention.

All U.S. provisional and non-provisional patent applications andpublications mentioned above are incorporated by reference in theirentirety for all purposes.

1-9. (canceled)
 10. A semiconductor package comprising: (a) a leadframestructure comprising a die attach region and plurality of leads; (b) amolding material molded around at least a portion of the leadframestructure, and wherein the molding material comprises a window; and (c)a semiconductor die comprising an edge mounted on the die attach region,wherein the semiconductor die is within the window, and wherein a gap ispresent between the edge of the semiconductor die and the moldingmaterial.
 11. The semiconductor package of claim 10 wherein theleadframe structure comprises copper.
 12. The semiconductor package ofclaim 10 wherein the semiconductor die comprises a vertical powertransistor including a source region, a gate region, and a drain region,wherein the source region and the gate region are proximate the dieattach region and the drain region is distal to the die attach region.13. The semiconductor package of claim 10 wherein the semiconductorpackage comprises bump and solder joints between the semiconductor dieand the leadframe structure.
 14. The semiconductor package of claim 10wherein the window has dimensions that are greater than lateraldimensions of the semiconductor die.
 15. The semiconductor package ofclaim 10 wherein the molding material comprises an epoxy moldingmaterial.
 16. The semiconductor package of claim 10 wherein the windowis a first window and wherein the molding material comprises a secondwindow, the second window exposing a surface of the leadframe structureopposite to the die attach region.
 17. The semiconductor package ofclaim 16 further comprising a heat sink coupled to the leadframestructure through the second window.
 18. The semiconductor package ofclaim 10 further comprising an array of joints coupling thesemiconductor die and the leadframe structure, wherein the array ofjoints comprises a solder or non-solder bump material and a solder pastematerial including different melting temperatures.
 19. An electricalassembly comprising: a semiconductor package comprising (a) a leadframestructure comprising a die attach region and plurality of leads, (b) amolding material molded around at least a portion of the leadframestructure and wherein the molding material comprises a window, and (c) asemiconductor die comprising an edge mounted on the die attach region,wherein the semiconductor die is within the window, and wherein a gap ispresent between the edge and the molding material; and a circuitsubstrate, wherein the semiconductor package is mounted to the circuitsubstrate.
 20. The electrical assembly of claim 19 further comprisingsolder coupling the semiconductor die to the leadframe structure. 21.The semiconductor die package of claim 10 wherein the gap is presentaround all edges of the die.
 22. The semiconductor die package of claim12 wherein the gap is present around all edges of the die.
 23. Thesemiconductor die package of claim 13 wherein the gap is present aroundall edges of the die.